My customer want to know a criteria for ripple on voltage rail to build a their custom board.
They are using i.MX6Dual and plan to migrate i.MX6Solo.
There is a following description that mentioned about reducing ripple on the voltage in P2 of schematic's SDP (SPF-27392_C5.pdf).
It is critical that the bulk and decoupling capacitors placed on the VDDARM_CAP, VDDARM23_CAP, VDDSOC_CAP
and VDDPU rails be placed directly underneath the processors.
Development testing has shown that proper placement of the capacitors can reduce ripple on the voltage rails by as
much as 50% compared to placing capacitors outside the physical boundaries of the processor. These will
result in more stable processor operations.
I understand it can reduce the ripple on the voltage rail whether the placement is outside the physical boundaries of the processor or not.
However, my cutomer and I It does not know whether the ripple's allowable range.
Do you have any data for it ?
If you have, please provide me and please also provide us a measurement condition.