We just noticed that the Table 36. DDR2 Input AC Timing is quite narrow.
For example, when the EMI clock is 200MHz, the range of input skew is 0.4 - 0.75ns and the range of input hold time is 2.0 - 2.25ns. (IMX28CEC Rev.3, 07/2012)
In contrast, the same parameters of i.MX50 are not so strict. (e.g. IMX50CEC does not define minimum input skew and maximum input hold time.)
In our board, tDQSQ of all DQ signals were ca. 0ns, definitely out of the range.
But the board is working well and memory test program (mtest) shows no error.
So we are suspecting that the data shown in IMX28CEC is wrong.
Does anyone know anything about it?