Section 184.108.40.206 of K60P144M150SF3RM (http://cache.freescale.com/files/microcontrollers/doc/ref_manual/K60P144M150SF3RM.pdf) details the flash structure. For the chip we are using, the MK60FX512VLQ15, but the table in the section seems to show something different to the text.
Could anyone clarify this for me?
For our chip the text says there are 5 blocks,
• For devices that contain FlexNVM: 2 blocks of program flash consisting of 4 KBsectors
• For devices that contain FlexNVM: 2 blocks of FlexNVM consisting of 4 KB sectors
• For devices that contain FlexNVM: 1 block of FlexRAM
But the table only references three (summarised below),
|Block 0 PFlash||Block 1 FlexNVM||FlexRAM|
|0x0000_0000 – 0x0007_FFFF||0x1000_0000 – 0x1007_FFFF||0x1400_0000 – 0x1400_3FFF|
Is the PFlash & FlexNVM actually 2 blocks of 256kB from [0x...0_0000 to 0x...3_FFFF] and [0x...3_FFFF to 0x...7_FFFF]?
If they are 2 blocks of 256kB can you therefore, in PFlash execute code from the lower block an write to the upper block at the same time. As described in section 30.4.8 Read while write (RWW)?