PETE SNYDER

MCF5282 FlexCAN receive masks corrupted

Discussion created by PETE SNYDER on Jan 29, 2008
Latest reply on Oct 20, 2009 by sandeep sudi
I am using the FlexCAN controller on the MCF5282 configured as follows:

MB 0-7 = Tx Buffers
MB 8-13 = Rx Buffers each configured with different ID_HIGH, ID_LOW
MB14-15 are set to NOT ACTIVE

Each Message Buffer has a different interrupt priority ( MB 0 is the highest and MB 13 is the lowest ).  The Wakeup, Error, and BusOff Interrupts (none of which I have seen) all have different prioirities as well.


When I configure RXGMASK to be 0x00000000 (i.e listen for all messages), I do not have any problems transmitting and receiving any message.  However, when I configure RXGMASK to only look at the bits I care about, I run into certain problems.

For example, traffic coming into MB 11 will work work fine for a while and then suddenly switch to MB 8.  Meanwhile, the traffic that was coming into MB 8 is no longer received until a reboot.  However, if I configure the software to never transmit any messages, this problem never occurs.  The trasmits always work no matter what happens to the receive MBs.


So it seems to be some interaction between transmitting and receiving where the ID_H and ID_L masks for the input message buffers are being corrupted.


Here is some pseudo code of what we are doing:

input_interrupt()
{
  disable interrupts
  read the MB CONTROL register to lock the MB
  read ID_H (16 bit)
  read ID_L (16 bit)
  read the data (byte access)
  clear the IFLAG bit
  read the TIMER to unlock the MB
  reenable interrupts

  do the work on the data
}

tx()
{
  write NOT_ACTIVE (0x0080) to CONTROL register
  write ID_H (16 bit)
  write ID_L (16 bit)
  write data (byte access)
  write (TRANSMIT_ONCE | data_length) to control register
}

Has anyone seen any problems like this or have any suggestion on how to prevent this from happening?

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