KL16 LPTMR clock synchronization in Low Power Modes

[CiaranMacA_hkc]

Hi All,

I am running the LPTMR off of the LPO and using it to wake up from VLPS (and sometimes, via LLWU, from LLS). In both cases I notice that the period is slightly longer in this sencario than it is when I do not drop into low power mode at all (i.e stay in RUN mode). The difference appears to be one clock cycle of the LPO which I'm using to drive the LPTMR without any pre-scaler.

The RM mentions the loss of a clock cycle or two when STARTING the LPTMR but there is no mention of a lost cycle when emerging from a stop mode.

I am aware of the variation in LPO accuracy to begin with (+- 10% in Datasheet)  but I only need accuracy to within 1% over a ten minute period and for that I calibrate my LPO regularly by driving an accurate edge from another chip on my design into GPIO and counting edges etc. The result is easily good enough for my application but the difference in behaviour of the LPTMR between run mode and the low power modes came as a surprise.

Can anyone explain if what I'm seeing is indeed a sync issue? If yes, why would a re-sync be needed after wakeup? I expected the LPTMR, once started, to run away happily from the LPO without any glitches.

Thanks,

Ciarán

[CiaranMacA_hkc]

UPDATE: Further evidence suggests this is not a clock sync issue. I did an experiment whereby I set the LPTMR to wakeup every 100ms. Running off the LPO. I compared a duration of ten periods with and without enterring VLPS. The difference was about 8ms. In this interval there were what, 10 sleeps and wakeups.

Now I reset the LPTMR to wakeup every 500ms. Again running off the LPO. Now compare a duration of two periods (approx 1s) with and without entering VLPS. Again the difference is 8ms. So it looks like it is not a sync issue introduced at wakeup, but simply the fact that the LPO clock appears to run slower when the device is sitting in VLPS than it does when the system is running.

Any explanation?

Thanks,

Ciarán

[CiaranMacA_hkc]

UPDATE: I actually brought the LPO out on a pin via CLKOUT. It's clear - when the part is in STOP mode : 1.010 kHz, when the part is in VLPS mode : 1.002kHz. So the difference is about 8% slower when in a low power stop mode. I wonder why is that? Is it because the LPO is an RC and the turning down of the regulator for low power modes affects it? I don't know.

[CiaranMacA_hkc]

UPDATE: I have now discovered that the slow IRC is also running slower in Low Power modes. By about the same amount - just under 1%. What is going on?

[isaacavila]

Hello Ciaran,

Could you please attach your code in order to validate your results?

Thank you!

Best Regards,

Isaac

[isaacavila]

Hi Ciaran,

Could you please attach your code?

Best Regards,

Isaac