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KL16 LPTMR clock synchronization in Low Power Modes

Question asked by Ciaran Mac Aonghusa on Sep 29, 2015
Latest reply on Oct 29, 2015 by isaacavila

Hi All,


I am running the LPTMR off of the LPO and using it to wake up from VLPS (and sometimes, via LLWU, from LLS). In both cases I notice that the period is slightly longer in this sencario than it is when I do not drop into low power mode at all (i.e stay in RUN mode). The difference appears to be one clock cycle of the LPO which I'm using to drive the LPTMR without any pre-scaler.


The RM mentions the loss of a clock cycle or two when STARTING the LPTMR but there is no mention of a lost cycle when emerging from a stop mode.


I am aware of the variation in LPO accuracy to begin with (+- 10% in Datasheet)  but I only need accuracy to within 1% over a ten minute period and for that I calibrate my LPO regularly by driving an accurate edge from another chip on my design into GPIO and counting edges etc. The result is easily good enough for my application but the difference in behaviour of the LPTMR between run mode and the low power modes came as a surprise.


Can anyone explain if what I'm seeing is indeed a sync issue? If yes, why would a re-sync be needed after wakeup? I expected the LPTMR, once started, to run away happily from the LPO without any glitches.