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TWR-K70 MSD HOST Bootloader : PLL error

Question asked by arnogir on Sep 29, 2015
Latest reply on Oct 7, 2015 by arnogir

Hello,

 

I'm using the K70 bootloader found here:

 

TWR-K70 MSD HOST Bootloader based on AN4368 source code

 

I have already tested it on the board without any problem.

Now I want re test the boot.

 

Then I compile, flash with the P&E, all work correctly.

 

Now I unplug the P&E to Run the board in standalone.

Board do nothing.

 

If I "Attach" the debugger, code is stay here in the following while(1). Anybody know where can come from my problem?:

in P3.c, _bsp_platform_init

 

 

 /* Initialize PLL0 */
 /* PLL0 will be the source for MCG CLKOUT so the core, system, FlexBus, and flash clocks are derived from it */ 
 mcg_clk_hz = pll_init(OSCINIT,   /* Initialize the oscillator circuit */
   OSC_0,     /* Use CLKIN0 as the input clock */
   CLK0_FREQ_HZ,  /* CLKIN0 frequency */
   LOW_POWER,     /* Set the oscillator for low power mode */
   CLK0_TYPE,     /* Crystal or canned oscillator clock input */
   PLL_0,         /* PLL to initialize, in this case PLL0 */
   PLL0_PRDIV,    /* PLL predivider value */
   PLL0_VDIV,     /* PLL multiplier */
   MCGOUT);       /* Use the output from this PLL as the MCGOUT */
 /* Check the value returned from pll_init() to make sure there wasn't an error */
 if (mcg_clk_hz < 0x100)
  while(1);

 

Edit:

For information, in pll_init, return value is 0x11:

 

if (MCG_S & MCG_S_IREFST_MASK) return 0x11; // check bit is really clear and return with error if not set

I'm using the same as Tower K70 system (with external quartz of 12MHz).

I don't know if following configuration is Ok for that:

 

 



#define CLK0_FREQ_HZ  50000000
#define CLK0_TYPE           CANNED_OSC



#define CLK1_FREQ_HZ        12000000
#define CLK1_TYPE           CRYSTAL

/* Select Clock source */
/* USBHS Fractional Divider value for 120MHz input */
/* USBHS Clock = PLL0 x (USBHSFRAC+1) / (USBHSDIV+1)       */
#define USBHS_FRAC    0
#define USBHS_DIV     SIM_CLKDIV2_USBHSDIV(1)
#define USBHS_CLOCK   MCGPLL0


/* USB Fractional Divider value for 120MHz input */
/** USB Clock = PLL0 x (FRAC +1) / (DIV+1)       */
/** USB Clock = 120MHz x (1+1) / (4+1) = 48 MHz    */
#define USB_FRAC    SIM_CLKDIV2_USBFSFRAC_MASK
#define USB_DIV     SIM_CLKDIV2_USBFSDIV(4)




/* Select Clock source */
#define USB_CLOCK   MCGPLL0
//#define USB_CLOCK   MCGPLL1
//#define USB_CLOCK   MCGFLL
//#define USB_CLOCK   PLL1
//#define USB_CLOCK   CLKIN


/* The expected PLL output frequency is:
 * PLL out = (((CLKIN/PRDIV) x VDIV) / 2)
 * where the CLKIN can be either CLK0_FREQ_HZ or CLK1_FREQ_HZ.
 * 
 * For more info on PLL initialization refer to the mcg driver files
 */

#define PLL0_PRDIV      5

#define PLL0_VDIV       24

#define PLL1_PRDIV      5

#define PLL1_VDIV       30

#endif



extern uint32_t ___VECTOR_RAM[];

 

 

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