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PWM output in MQX using IAR Embedded Workbench

Question asked by Joshua Weitz on Sep 28, 2015
Latest reply on Sep 28, 2015 by Joshua Weitz

I am trying to setup a PWM output in MQX using IAR Embedded Workbench. I found this project, DRM135SW which has some example code for setting up the FTM for PWM. I tried setting up my init function in a similar way, but when I try to step though the init the project it crashes when I try to access the FTM 3 registers. I can't find any documentation on setting this stuff up, and MQX does not seem to have any build in functions for accessing the FTM. Has anyone done this successfully before?

 

bool UI_vib_init()

{

      /* check write protection */

      if(FTM3_FMS & FTM_FMS_WPEN_MASK)

      {

        FTM3_MODE &= ~FTM_MODE_WPDIS_MASK; /* Disable write protection */

      }

      FTM3_MODE |= FTM_MODE_FTMEN_MASK;

      FTM3_CONF |= FTM_CONF_BDMMODE(3); // counter run in BDM mode

      FTM3_MODE |= FTM_MODE_FAULTM_MASK | FTM_MODE_FTMEN_MASK;

      /* Set PWM frequency; MODULO = Fclk/Fpwm */

      FTM3_MOD = MODULO;

      FTM3_CNTIN = 0x00;

 

 

      FTM3_SYNCONF |= FTM_SYNCONF_SYNCMODE_MASK; // should be set enhanced PWM sync mode

      /* CTNMAX = 1 - PWM update at counter in max. value */

      FTM3_SYNC |= FTM_SYNC_CNTMAX_MASK;

      FTM3_SYNC |= FTM_SYNC_SWSYNC_MASK;  

 

 

     

       /* Disable all channels outputs using the OUTPUT MASK feature.

      However, the output pins are still driven as GPIO since the

      channel mode is set to FTM channel disabled after RESET */

      FTM3_OUTMASK = FTM_OUTMASK_CH4OM_MASK;

    

      /* COMBINE = 1 - combine mode set

      COMP = 1 - complementary PWM set

      DTEN = 1 - deadtime enabled

      SYNCEN = 1 - PWM update synchronization enabled

      FAULTEN = 1 - fault control enabled */ 

      FTM3_COMBINE = FTM_COMBINE_FAULTEN1_MASK | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_DTEN1_MASK

                    | FTM_COMBINE_COMP1_MASK | FTM_COMBINE_COMBINE1_MASK;

     

      /* polarity setting, set for active low */

      FTM3_POL = FTM_POL_POL3_MASK;

     

      /* Dead time = 1 us for 48 MHz core clock */

      //FTM3_DEADTIME = 138;

      /* Initial setting of value registers */

      FTM3_C4V = MODULO/2;

 

 

      /* SWSYNC = 1 - set PWM value update. This bit is cleared automatically */

       FTM3_SYNC |= FTM_SYNC_SWSYNC_MASK;  

 

 

      /* Main loop */

      /* ELSnB:ELSnA = 1:0 Set channel mode to generate positive PWM

      Note:

      1. From this moment the output pins are under FTM control. Since the PWM output is disabled by

      the FTM3OUTMASK register, there is no change on PWM outputs. Before the channel mode is set,

      the correct output pin polarity has to be defined.

      2. Even if the odd channels are generated automatically by complementary logic, these channels

      have to set to be in the same channel mode. */

     

      FTM3_C4SC |= FTM_CnSC_ELSB_MASK ;

     

      FTM3_EXTTRIG |= FTM_EXTTRIG_INITTRIGEN_MASK;

    

      FTM3_MODE |= FTM_MODE_INIT_MASK;

      /* Set system clock as source for FTM0 (CLKS[1:0] = 01) */

      FTM3_SC |= FTM_SC_CLKS(1); 

      //PORT for FTM0 initialization

      PORTC_PCR8 = PORT_PCR_MUX(IO_MUX_ALT4);

 

 

      return TRUE;

}

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