Dear Sir or Madam,
Hello.I have a question about CSI_PIXCLK of Gated Clock Mode Timing in i.MX6SL.
Refer to "220.127.116.11.1 Gated Clock Mode Timing" in IMX6SLCEC_Rev.3.
There is below description.
"The pixel clock, CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted."
Is it possible to stop CSI_PIXCLK (PIXCLK) from external device, as long as HSYNC is de-asserted?