I am working on i.MX6 sabre-sd board. We have interfaced an FPGA to the board [Sabre SDB] over EIM bus. The FPGA provides a register bank that needs to be accessed from the i.MX6.
The EIM is configured for 16-bit Multiplexed Address/Data Synchronous mode communication [ DSZ=001, MUM=1 and AUS=1]. I am able to establish communication with the FPGA over EIM bus and access the FPGA memory . But we observed that the register access on the FPGA succeeds only for even addresses and fails for odd addresses.
For example, read/write to the FPGA memory at the offset 0xC0DE is successful. But read/write access to the FPGA memory at the offset 0x5555 fails.
When we connected a logic analyzer to verify the activity on the address and data lines AD[15:0], the following are the observations:
* During attempts to access the odd address at 0x5555, we see 0x5554 being sent out on the address bus. This is the case with other odd addresses also.
* In other words, AD0 always remains 0 (low).
* Access to any even address succeeds.
Based on the above observations, we assume that this issue happens only when access to odd address is attempted.
For the given configuration, is this an expected behavior?
How can we access odd address location on FPGA? Or should all the register offsets be aligned evenly ?
Any pointers regarding this would be helpful.
Thanks in advance for your time.