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i.MX6 SoloX Cortex-M4 clock frequency

Question asked by Zvonimir Mandić on Sep 22, 2015
Latest reply on Sep 23, 2015 by Zvonimir Mandić

Simple question: is M4 frequency set to 227 MHz by default in u-Boot boot parameters?

 

I wrote a simple test application with gpio output to measure M4 frequency. Applications code goes something like this:

          set_gpio

          nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;

          clear_gpio

          nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;

          set_gpio

          nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;

          clear_gpio

          nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;

       

Basically I'm measuring execution time of 10 nop instructions. The difference in execution time I'm getting is 540 ns which gives me 54 ns per instruction (should be between 4 and 5 ns).

Cortex-m4 generic user guide states: "NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it

from the pipeline before it reaches the execution stage.", so I have written a similar example with "teq" (test equal) assembly instruction. Difference in execution when using teq is 1 us (which gives 100 ns per instruction).

 

By reading CCM registers it can be seen that M4_CLK_ROOT uses PLL3_PFD3 divided by 2 so frequency should be 227.35 MHz.

Register values are:

PLLPFD3   addr=0x420C80f0        value=0x5351504c

PLL3          addr=0x420C8010       value=0x80003000

CHSCCDR addr=0x420C4034       value=0x00021148

 

 

Test application runs from DDR from address 0x10000000. It's size is smaller than cache so I think the whole code should be loaded and executed from L1. Same results are when A9 is in u-Boot and when A9 loads and runs linux.

 

In this application I'm using M4's SysTick with reload value 227232 (or 1 ms). I have written a handler which also toggles gpio. With this everything looks fine (measure gives exactly 1 ms period).

 

Also I have found a function in linux kernel in location [KERNEL]/arch/arm/mach-imx/clk_imx6sx.c called imx6sx_set_m4_highfreq(bool high_freq). Does this function set M4 to higher frequency? Maybe it's not called with high_freq=1.

 

 

Thanks

 

EDIT: System boot sets PLL3 frequency to 480 MHz.

Are there any internal clock setup registers in M4? Maybe some divider or bypass is enabled.

 

EDIT2: i.MX 6SoloX Applications Processor Reference Manual on page 466 Table 13-2. Platform Clock Descriptions lists all possible M4 clock inputs:

sw_clk_tck      Single Wire/ JTAG Test Clock

trace_clk_in    TPIU - Trace Port Clock

tcmc_hclk       TCMC Clock

cm4_hclk        Gated CPU Clock. Platform output "cm4_gate_hclk" can be used as the enable signal.

cm4_fclk         Free-running CPU Clock

ipg_clk_nic     Gated PL301 Clock

 

Where is input clock selected? Does M4_CLK_ROOT need additional configuring outside of CCM?

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