Hi community,
I have a question about i.MX6 Series DDR design.
Please see chapter 2.5.1 in IMX6SLHDG Rev.1.
It says as below.
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• JEDEC DDR3 memory restrictions are:
– No restrictions for complete byte lane swapping
– DQS and DQM must follow lanes
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I don't understand the meaning of the above "complete byte lane swapping".
It supports the swapping as the following image?
Best Regards,
Satoshi Shimoda
Solved! Go to Solution.
HI Satoshi
I think you are right and also DQS and DQM must follow lanes.
Best regards
igor
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HI Satoshi
I think you are right and also DQS and DQM must follow lanes.
Best regards
igor
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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