I have a question about i.MX6 Series DDR design.
Please see chapter 2.5.1 in IMX6SLHDG Rev.1.
It says as below.
• JEDEC DDR3 memory restrictions are:
– No restrictions for complete byte lane swapping
– DQS and DQM must follow lanes
I don't understand the meaning of the above "complete byte lane swapping".
It supports the swapping as the following image?