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i.MX6 series DDR complete byte lane swapping.

Question asked by Satoshi Shimoda on Sep 14, 2015
Latest reply on Sep 14, 2015 by igorpadykov

Hi community,


I have a question about i.MX6 Series DDR design.

Please see chapter 2.5.1 in IMX6SLHDG Rev.1.

It says as below.


• JEDEC DDR3 memory restrictions are:

– No restrictions for complete byte lane swapping

– DQS and DQM must follow lanes



I don't understand the meaning of the above "complete byte lane swapping".

It supports the swapping as the following image?





Best Regards,

Satoshi Shimoda