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MIPI CSI receiver problem

Question asked by Kristoffer Glembo on Sep 11, 2015
Latest reply on Sep 14, 2015 by Yuri Muhin

Hi everybody,


I'm doing board bring up on a board with a FPGA MIPI CSI transmitter and the IMX6 as a receiver.


I'm having some trouble getting the MIPI CSI block in the IMX6 properly receive the signals from the FPGA. I've tried at 200 MHz and 400 MHz MIPI DPHY clock rate and the problem is the same. The MIPI_CSI_PHY_STATE register goes from 0x200 (FPGA not transmitting) to 0x6F0 when the FPGA transmits data (i.e. not receiving any clock, clock and data lanes in stop state). I'm using 4 data lanes.


When operating at 200 MHz I write 0x14 to the DPHY clock register during reset. For 400 MHz I've used 0x6. Since this register is undocumented I'm unsure if these are the correct values, can you confirm?


What can cause this type of issue?