Can't get K20 MCG FLL Mode to be selected (MCG_S = xxxx11xx instead of MCG_S = xxxx00xx).
1) MQX 4.20:
2) Based on twrk20d72m tower software
a) tower schematic calls out the PK20DX256VLL7, while the chip used is MK20DX256VMC10. Had to change the code to support this chip (MK20D10.h instead of MK20D7.h).
b) RTC crystal is used to drive everything (XTAL32 and EXTAL32, 32.768Khz). XTAL0 and EXTAL0 are not connected. The code was changed to support this configuration (Processor Expert 10.4.0). Attached is the bsp code change for the MCG FLL Mode change.
3) no external FLASH, DDR, or MRAM.
4) IAR IDE and I-Jet debugger (7.40 for ARM).
1) IAR IDE and I-Jet debugger seems to work.
2) most K20 register values (debugger) are 0xCDCDCDCD (e.g. MCG_xxx, RCM_xxxx, SIM_xxx). Clearly this is not correct. debugger artifact? K20 problem? The code does seem to read and react to these values. Perhaps this problem is related to Reset signal (see below). The debugger claims the K20 registers are updated every second.
3) K20 Reset signal (J11) is toggling. 65us period, low for 63us and high for 2us. WDOG is disabled. Clock Monitors are disabled. VDD is 3.3V. Not using any low power modes. Removing the debugger doesn't change this behavior. Reset net is connected to JTAG (debugger) only, with a 10K pull-up.
4) Can't get K20 FLL Mode to be selected (MCG_S = xxxx11xx instead of MCG_S = xxxx00xx). Could be the 0xCDCDCDCD problem.
5) The XTAL32 and EXTAL32 pins have no voltages. I would expect about 1/2 voltage. I don't think the crystal will oscillate with zero volts.
I have checked the layout and schematic to make sure all the VDD and VSS are connected and found no problems.
Original Attachment has been moved to: K20_bsp.zip