I'm using a MK10DX64VLH7. Within the project I'm using the watchdog (no window mode) with the LPO as clock source, the timeout value is at 1000ms and the refresh will be every 16ms.
Now I want to disable the watchdog (because I want to set the Controller into sleep mode), so I'm writing a 0 to the WDOGEN Bit.
After that, there will be a while (1) loop (later, I want to set the Controller into vlls3).
Sometimes it happens, that I'm get a WDOG reset..... I can see this in the SRS0 Register.
After some tests, it seems that the WDOG will ignore the disable (WDOGEN = 0). Here is my test application, which will Trigger the WDOG reset very much:
1. refresh the WDOG
2. wait until WDOG->TMROUTL = 1
3. disable the WDOG (WDOGEN = 0, __DSB, __DMB)
4. read the WDOGEN (result = 0)
.... do some other things
5. read the WDOG->TMROUTL (result = 6 or 7)
6. while (1)
7. get the WDOG reset
in this application I'll get the WDOG reset in approximately 9 of 10 tests.
If I'm waiting for WDOG->TMROUTL > 3 (in step 2) everything is fine. In step 5 I'll read 0 - as expected and there will be no reset.
Does anybody know (or have an idea) where could be the problem, that the WDOG is resetting although it will be disabled?
I've read in the Manual (23.7.4 Watchdog Time-out Value Register Low), that there sometimes will be a delay about 4 watchdog clock cycles.....
"The time-out value of the watchdog must be set to a minimum of four watchdog clock
cycles. This is to take into account the delay in new settings taking effect in the watchdog
Could this be my problem? I thought no, because there is enough time to the WDOGEN = 0 to take effect (~990ms).
If you need any additional information, please let me know.
I'm very thankful for every information or idea, what could cause this behavior.