K70 SysTick Clock Source Bit

[pmcl]

Hi All,

I'm using the K70 SysTick Timer and referred to the K70P256M150SF3EM manual, section 3.2.1.2 on page 85 which says that the CLKSOURCE bit in the SysTick Control and Status Register is always set to select the core clock. However, if I have this line in KDS3.0.0:

  SYST_CSR = (SysTick_CSR_ENABLE_MASK | SysTick_CSR_TICKINT_MASK);

it does not generate an interrupt - which means SysTick is not ticking. If I use:

  SYST_CSR = (SysTick_CSR_ENABLE_MASK | SysTick_CSR_TICKINT_MASK | SysTick_CSR_CLKSOURCE_MASK);

I do get an interrupt.

I thought the value of CLKSOURCE was always set and not writable, so the first bit of code is all that is needed?

Since that code writes a 0 to the CLKSOURCE bit, does that mean it is writable, and therefore not always "set"?

Thanks!

[mjbcswitzerland · Accepted solution]

Peter

The core clock is selected by default but there is nothing stopping you writing it to 0 and thus disabling it.

See also ARM Information Center

Regards

Mark

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K70: µTasker Kinetis TWR-K70F120M support  / µTasker EMCRAFT K70F120M support

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[pmcl]

Thanks Mark.

I was relying on the Freescale documentation and didn't go "down a level" to the ARM documentation, which makes it clear that the CSR register is set to 0x000_0004 coming out of reset if the alternate reference clock is not present.

I think Freescale should change the line:

"- The CLKSOURCE bit in SysTick Control and Status register is always set to select the core clock."

so that it says "initialised to 1 after a reset".