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strange behaviour with chip select bounds on DDR controllers

Question asked by Frank Dischner on Sep 8, 2015
Latest reply on Sep 9, 2015 by Bulat Karymov

Hello,

 

I'm working with the P4080DS and trying to configure the two DDR controllers to access the same memory space but without interleaving. I have one LAW configured with address 0x00000000 and size of 1GB assigned to DDR controller 1 and a second LAW with address 0x40000000, 1GB and assigned to DDR controller 2. This works fine and I can access all 2GB of RAM, however, I want the second gigabyte to address the same physical RAM as the first gigabyte. In other words, I want both controllers to always use cs0 and never cs1. No matter how I configure the cs bounds, I always read 0xdeadbeef (the initialization value) from addresses above 0x40000000 so it seems that the second controller is always using cs1. If I configure only a single LAW with size 2GB to a single controller (doesn't matter which one) and cs0 bounds to 0x00-0x7f, then I see the memory mirrored as I expect. Also, if I use a single controller with cs0 bounds 0x00-0x3f and cs1 bounds 0x40-0x7f, then I can access the entire 2GB of physical memory. It's only when I have both controllers enabled that the chip select bounds seem to be ignored. Any idea what I might be doing wrong?

 

Thanks

-Frank

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