AnsweredAssumed Answered

Maximum ADC sampling rate when triggered by PDB

Question asked by Sergei Sharonov on Sep 4, 2015
Latest reply on Sep 8, 2015 by jeremyzhou


Kinetis ADC takes longer to acquire the first sample in a sequence due to SFCAdder effect. Apparently when triggering ADC by PDB this first sample limits maximum sampling rate. If PDB interval is shorter than this first extended ADC sample (but longer then subsequent "normal" samples), PDB will stop and not trigger until the error is cleared from PDB_CHnS register.

In my case this changes required number of cycles per sample from 27 to ~32, e.g. 19% drop in maximum sampling rate. Is there  a way to avoid this? Note that I cannot free-run ADC as I use PDB to synchronize ADC and DAC.