AnsweredAssumed Answered

FlexBus operation with limited pins mapped?

Question asked by Jeff Bingham on Sep 4, 2015
Latest reply on Sep 9, 2015 by jeremyzhou

I am considering using a K60-series processor as a generic test control processor, and am looking to use as much of the configured functionality as possible alongside a parallel [FlexBus] interface. To maximise other functionality, I am looking to restrict the mapped FlexBus pins to FB_AD0 to FB_AD15 [along with control signals and some chip-selects], and will interface this with 8-bit & 16-bit peripherals as needed. This means that the pins which would normally be associated with FB_AD16 to FB_AD31 are mapped to other functions.

 

I recognise that I'd need to set CSCR[BLS] = 1 to ensure that the data bus is mapped to the lower FB_AD lines.

 

Key question is whether I will introduce problems by not bringing out at least a 32-bit bus on external pins? For example: in order to read from 8-bit/16-bit devices, I would effectively have to do a 32-bit read. With the upper 16 bits 'not mapped to pins', what appears on these upper bits as they are read in by the FlexBus function? If I needed further I/O [and only needed - in some implementations - to support 8-bit wide peripherals], is there anything stopping from further reducing this external pin mapping to (say) a 12-bit interface [12-bit address/8-bit data]?

Outcomes