FlexBus operation with limited pins mapped?

[jeffbingham]

I am considering using a K60-series processor as a generic test control processor, and am looking to use as much of the configured functionality as possible alongside a parallel [FlexBus] interface. To maximise other functionality, I am looking to restrict the mapped FlexBus pins to FB_AD0 to FB_AD15 [along with control signals and some chip-selects], and will interface this with 8-bit & 16-bit peripherals as needed. This means that the pins which would normally be associated with FB_AD16 to FB_AD31 are mapped to other functions.

I recognise that I'd need to set CSCR[BLS] = 1 to ensure that the data bus is mapped to the lower FB_AD lines.

Key question is whether I will introduce problems by not bringing out at least a 32-bit bus on external pins? For example: in order to read from 8-bit/16-bit devices, I would effectively have to do a 32-bit read. With the upper 16 bits 'not mapped to pins', what appears on these upper bits as they are read in by the FlexBus function? If I needed further I/O [and only needed - in some implementations - to support 8-bit wide peripherals], is there anything stopping from further reducing this external pin mapping to (say) a 12-bit interface [12-bit address/8-bit data]?

[nicholasf]

Why would you have to do a 32-bit read when Flexbus is configured with 8 or 16 bit bus width (using the FB_CSCRn register)?  I have used Flexbus with 16 bit communications and never had to read 32-bit width; there is no requirement for read alignment or size as far as I know; the application simply reads whatever datatype it is programmed to from a location in the Flexbus' address range, and receives a value (, I believe the default is zero if there are unconfigured pins, but I could be incorrect).  There is also nothing stopping you from only configuring 12 pins for addressing and 8 bits for data with Flexbus, in fact, that is exactly what is done when the 8-bit width is selected, and the correct 12 pins are configured (by their corresponding PCRs) for Flexbus.

[jeffbingham]

I think you are right: I've just been reading through the user manual again and it indicates that a 32-bit read from [for example] an 8-bit register would read four consecutive addresses. I also noted that not all 32 of the FB_AD pins are brought out on all devices [eg: 100-pin LQFP K64 device], which implies that what I am looking to do is already enforced in at least some implementations. I understand that the device still reads into 32-bit registers [so would guess that the unused bits in the register are zeroed]. Thanks for the reply.

[jeremyzhou]

Hi Jeff,

Of course, the FlexBus module support continuous read or write through the 8-bit or 16-bit port to complete a 32-bit data transfer.

In the reference manual, you can learn more information about the data-byte alignment and physical connections.
Have a great day,
Ping

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