Currently I'm involving DDR3 validation.
Here is the information about my setup.
Processor : MCIMX6U6AVM08AC
DDR3 Memory : MT41K128M16JT-125AITK
DDR3 Clock frequency : 400MHz
ARM Frequency : 800MHz
Chip Select used : CS0
No of chip’s DDR3 chips used : 4 no’s connected in fly by topology
Oscilloscope : 16 GHZ DPO
Probing Points on the Processor:
Clock (Channel C1) DDR_CLK_0 & DDR_CLK#_0
Data Strobe (Channel C2) DDR_SDQ0 & DDR_SDQ#0
Data 0 (Channel C3) DDR_DATA0
We have done the below methods to make slew rate (SRQdiff & SRQse) pass in DDR Read Burst,
- Modified the ODT Termination with different values like 30 ,40 , 60 Ohms etc
- Modified the Drive strength of the DDR in MR1 register for DDR3
- Modified the Drive strength of Processor DQS , DQ which we are probing.
PS: We have calibrated the board with DDR3 stress test tool.
We are getting failure DQS slew rate measurements.
Can any one please help us to solve this problem.