Hi All,
Currently I'm involving DDR3 validation.
Here is the information about my setup.
Processor : MCIMX6U6AVM08AC
DDR3 Memory : MT41K128M16JT-125AITK
DDR3 Clock frequency : 400MHz
ARM Frequency : 800MHz
Chip Select used : CS0
No of chip’s DDR3 chips used : 4 no’s connected in fly by topology
Oscilloscope : 16 GHZ DPO
Probing Points on the Processor:
Clock (Channel C1) DDR_CLK_0 & DDR_CLK#_0
Data Strobe (Channel C2) DDR_SDQ0 & DDR_SDQ#0
Data 0 (Channel C3) DDR_DATA0
Observations:
We have done the below methods to make slew rate (SRQdiff & SRQse) pass in DDR Read Burst,
PS: We have calibrated the board with DDR3 stress test tool.
We are getting failure DQS slew rate measurements.
Can any one please help us to solve this problem.
Hello,
You may try simulation a) on die and b) on pin.
And quite acceptable waveforms on die look not so good on pin,
just as yours. It is important to have proper signals on die.
Have a great day,
Yuri
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Hi,
according to the picture you do have a reflection on your measured signal. Most likly due to your testpoint. So this is a measurement artefact.
Are you using any interposer and do any de-embedding ?
But I have to admit, that I do not understand the Report from the Tek scope.
standard slew rate on DDR2 is still 1v/ns. not sure what the 5V/ns and 10V/ns really stand for and I'm also not sure why some of them are pass if you do not reach the low limit ..
But I have to admit, that I usually work with the tools from other scope vendors.
I would not expect that Tek does have better tools, so expect also wrong measurements ..
Hermann
Hi Hermann,
Thanks for your reply.
I don'see any wrong pass/fail here, I think that is -ve values right so more negative value means low and less negative value means high right?
So it seems measurement are correct.
PS: We able to make write burst pass.
Any recommendations ?
Thanks for your support.