As we are validating the DDR3 read and write burst, we could see failures in DQS output slew rate (SRQdiff) and data output slew rate (SRQ-se).
So, we are thinking to change the drive strength of DDR3 through MRS commands (MR1 register : M5&M1).
To enable/modify the DDR drive strength, we have modified the "flash_headers.S" from u-boot,
MXC_DCD_ITEM(75,MMDC_P0_BASE_ADDR + 0x01C, 0x00048031)
MXC_DCD_ITEM(75,MMDC_P0_BASE_ADDR + 0x01C, 0x00048011)
Then I'm not able to get any prints on tera term, its just completely hang.
Can anyone suggest on what to do for making DDR3 passing JEDEC standard and how to change the DDR drive strength for DDR3 and where & which file need to change .
PS: We have calibrated and written given calibrated data from DDR stress test tool.
Thanks for your support.