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multiple transaction ECSPI1 transfers on iMX6 very slow

Question asked by Karsten Keil on Sep 3, 2015
Latest reply on Sep 14, 2015 by alejandrolozano


I try to write a SPI protocol driver (kernel space) using Linux 3.10.70 kernel. The SPI transfer works so far, but serveral transfers to read or write registers on the  slave chips have long delays. Looking at the SPI signals I see that the CS signal is much too long, and here are also small waits between the transfered bytes.

I use 8MHz SPI clock speed.

The registers are all 8bit and one transaction consists of 4 bytes:


<addr write ctrl> <register addr> <data write ctrl> <data>


<addr write ctrl> <register addr> <data read ctrl> <data>

Example data read:


Complete transaction (same read):


You see that the chip select is much longer activ as needed, about 4us before SPI clock starts and about 40 us after the transaction did end.

My code for read is simple:

static u8 read_xhfc_spi(struct xhfc_spi *xs, u8 reg)


        int ret;


        xs->txd[0] = XSPI_ADDR | XSPI_WR | xs->dev_n;

        xs->txd[1] = reg;

        xs->txd[2] = XSPI_DATA | XSPI_RD;

        xs->spi_xfer.tx_buf = xs->txd;

        xs->spi_xfer.rx_buf = xs->rxd;

        xs->spi_xfer.len = 4;

        ret = spi_sync(xs->pdev, &xs->spi_msg);

        if (ret) {

                dev_err(&xs->pdev->dev, "error %d on spi_sync() for read 0x%02x\n", ret, reg);

                xs->rxd[3] = 0;


        return xs->rxd[3];



The xs->spi_msg is setuped as follows and reused every time:


    spi->bits_per_word = 8;
    /* initialise pre-made spi transfer messages */
    spi_message_add_tail(&xs->spi_xfer, &xs->spi_msg);



Do you have an idea, why this happens and how to change the behavior, or what I doing wrong ?