I'm currently working on a prototype design on the MCIMX6SLEVK. I'm interfacing with an external codec that can only be in I2S slave mode, and will be using an SSI module in master mode to interface with it. The catch is that we have an externally generated master clock (must be external for performance reasons), and all the I2S signals from the SSI must be derived from it. The plan is to bring in the master clock (24.576MHz = 512*48KHz) through the CLK1_P/N, set the PLL4 into bypass and set the bypass source to CLK1 and the divide and route it to the SSI. I would know how to do this on bare metal, but I'm using Linux for this project and haven't done this before. Could I get some guidance on how I would set this up. I'm pretty sure it revolves around some device tree tweaks, I'm just not sure exactly where to start and haven't been able to track down any documentation or examples that are close enough to what I'm doing.