We are using a iMX6Q with a MT42L128M64D2 1GB (two 512 MB dies) PoP memory.
I have some questions regarding the DDR mapping to choose. According to this page i.MX6DL LPDDR2 Support for L3.0.35_4.0.0 the fixed dual channel mapping is not recommended, why not?
Currently we are running with the RAM mapping fuse unprogrammed and thus in single channel mode. The odd thing is that it seems we can still reach all memory in this configuration. Accesses to 0x10000000 and 0x80000000 both work and seems not to be aliased. We setup both MMDC0-1 and configure 1 chip select per channel (size 512 MB). According to the user guide only MMDC0 is used in single channel mode, so how can this work?
I have programmed the fuse on one CPU to fixed 2x mapping and I am not able to find a good calibration value on the second channel at 396 MHz. If I go down to 352 MHz it works and the stress test passes. However other memory tests can still find errors. Could you review my MMDC config (see attached file) and suggest improvements? I have tried a lower drive strength but it seems to worsen the situation.
Original Attachment has been moved to: lpddr2_init.stress.zip