I'm currently working with MPC8569 processor board design. And i'm tottaly stuck in one thing. How to make proper fanout for address lines in DDR3 interface?
For DDQ-lines it's possible to do pin swapping, so this part don't make any trouble for me. But for address, control and clk signals this is unacceptable. They are tottaly mixed up with eachother, so i don't understand how to realize so-called 'fly-by' architecture.
If there some kind of reference designs with DDR3 fly-by topology for Freescale processors, please share with me a link. Or if there is some guide for this, i'll be very appreciated.
Thanks in advance.