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T2080 package  pin delays for DDR3 interface deskewing

Question asked by Marc Humphreys on Aug 27, 2015
Latest reply on Aug 28, 2015 by Bulat Karymov

Does Freescale provide pin delay information for the T2080 package so that we can deskew the DDR3 interfaces when matching the bits and strobe in the byte lanes? If not is there a spec for the maximum pkg induced skew per byte lane .