Does Freescale provide pin delay information for the T2080 package so that we can deskew the DDR3 interfaces when matching the bits and strobe in the byte lanes? If not is there a spec for the maximum pkg induced skew per byte lane .
The users should consider that all DDR signals are length matched within the package. So you need to provide length matching between pins of the T2080 and pins/pads of the SDRAM devices/modules.
