About Signal amplitude on DQ lines in i.MX6DQ.

[keitanagashima]

Dear All,

Hello. My customer found the Signal amplitude on DQ lines were small with DDR stress Test.

*Refer to attached file.

[Q1]

Does the output-characteristics of i.MX6D/Q cause this phenomenon?

[Q2]

Could you tell me this cause and workaround?

Best Regards,

Keita

[Yuri]

Hello, Keita !

  Perhaps, reason of different amplitudes is ODT. During write into DRAM, ODT in the memory

is activated. It changes impedance from Rtt_nom to Rtt_WR. Depending on the setting it changes

amplitude.   Please refer to section 44.10 (ODT Configuration) of the i.MX6 D/Q RM for more details

regarding ODT.

Have a great day,
Yuri

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[keitanagashima]

Dear Yuri,

Hello.Thank you for your reply.

>It changes impedance from Rtt_nom to Rtt_WR.

I confirmed the Rtt values and Rtt_nom value was same Rtt_WR.

"Rtt_nom = Rtt_WR = RZQ/4"

[Q1]

We want to know the reason with small amplitude of vibration (1st bit).

[Q2]

What setting should one do specifically to this problem?

Best Regards,

Keita

[Yuri]

Hello,

  Please try to disable DRAM ODT (at all).

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

My customer checked DQ signal lines with disable DRAM ODT (at all).

Refer to attached file (Measurement result).

But, the phenomenon didn't improve.

We found the ODT changing unrelated the problem.

Could you tell me the other solution?

Best Regards,

Keita

[Yuri]

  Keita, hi !

  Please check if i.MX6 ODT is disabled too.

Waveforms depends on probe measure point – is it DRAM pin ?

Moreover You may try simulation for both pin and die.

If die signal is correct – it is OK.

Regards,

Yuri.

[keitanagashima]

Dear Yuri,

Hello. Thank you for your reply.

>  Please check if i.MX6 ODT is disabled too.

The test situation is write only by high stress write test program.

So, we think that i.MX6 ODT isn't effect the waveform.

>Waveforms depends on probe measure point – is it DRAM pin ?

Yes. It is DRAM pin.

>Moreover You may try simulation for both pin and die.

>If die signal is correct – it is OK.

My customer didn't simulate on die. (Only pin).

And the JEDEC spec was defined at pin.

The phenomenon looks on SABRE-SDP, too.

Do you have other way to improve for 1st bit DQ amplitude?

Best Regards,

Keita

[Yuri]

Keita, hi !

> So, we think that i.MX6 ODT isn't effect the waveform.

  Nevertheless, it makes sense to try disabling i.MX6 ODT - to avoid its influence,

because of time, needed to switch on / off ODT. 

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

> Nevertheless, it makes sense to try disabling i.MX6 ODT - to avoid its influence,

> because of time, needed to switch on / off ODT.

OK. I requested my customer it.

The i.MX6's ODT setting is right below, isn't it?

"MMDC PHY ODT control register (MMDCx_MPODTCTRL)"

Best Regards,

Keita

[Yuri]

Yes, "MMDC PHY ODT control register (MMDCx_MPODTCTRL)"

~Yuri.

[keitanagashima]

Dear Yuri,

Hello. Sorry for my delay response.

We measured the waveforms with disabling i.MX6's ODT, too.

Refer to attached file (in English).

But, we didn't understand about result of measurement waveform.

We think that DDR ODT active & i.MX6 ODT no effect in write operation.

[Question]

Is DDR ODT active in attached file?

(DDR ODT looks no effect)

Why was i.MX6 ODT active?

(i.MX6 ODT looks active)

Is there a way to improve amplitude of 1st vibration?

Best Regards,

Keita

[Yuri]

Hello,

Please look at my comments below.

1.

> Is DDR ODT active in attached file? (DDR ODT looks no effect)

The fact, that the waveforms are not changed for DDR ODT ON/OFF cases

may be explained if :

1.1) illegal ODT programming ;
1.2) oscilloscope probe is located near i.MX6 (not near DDR part).

2.

> Why was i.MX6 ODT active? (i.MX6 ODT looks active)

2.1) correct ODT programming ;
2.2) oscilloscope probe is located near i.MX6.

3.

> Is there a way to improve amplitude of 1st vibration?

Please try to locate the probe near DDR during measurements.

Regards,

Yuri.

[keitanagashima]

Dear Yuri,

Hello.

Thank you for your reply.

My customer has already measured the location near DDR3.

And, refer to attached Customer's DDR3 settings.

I checked the MMDC1_MPODTCTRL reg.

But, I couldn't find the problem.

(My customer is using DDR3 with CS0 only.)

Best Regards,

Keita

[Yuri]

Hello,

You wrote, that  Rtt_Nom and Rtt_Wr are equal, but switching timing

between them may be important.

  It is possible to disable DDR3 ODT (both Rtt_Nom and Rtt_Wr) ?

Perhaps the issue concerns with the fact, that there are several DDR3 chips ;
in such case Rtt Wr is used for the one, that are affected, but the others, which
shares the same DQ/DQS/DM lines, are still terminated (with Rtt Nom).

Strictly speaking we need to calibrate memory system to avoid the signal integrity

issues. Was the memory tested after calibration and using optimal values ?

Regards,

Yuri.

[keitanagashima]

Dear Yuri,

Hello. Thank you for your reply.

> It is possible to disable DDR3 ODT (both Rtt_Nom and Rtt_Wr) ?

Yes. They have already tested it.

(Sorry for my poor description in previous document. I updated the attached document.)

Refer to "ODT_On_Off" sheet in attached file.

And, we measured it on SABRE-SD + freescale DDR Stress Test v2.20.

Same phenomenon was seen.

Refer to "SABRE-SD" sheet in attached file.

PS,

The phenomenon was not seen in i.MX6Solo/DualLite.

This occurred only i.MX6Dual/Quad.

Best Regards,

Keita

[Yuri]

Hi,

below are some points from app team :

the amplitude should be in spec per the datasheet.

4.6.3.2 DDR3/DDR3L Mode I/O DC Parameters

the output min is 0.8*OVDD. so the margin should be 0.2*1.5V=300mv.

from the wave form customer captured, the difference between the first DQS

signal and other is only about 100mv.

did they see the JEDEC violation after calibration?

Regards,
Yuri.

[keitanagashima]

Dear Yuri,

Hello. Thank you for your reply.

> from the wave form customer captured, the difference between the first DQS

> signal and other is only about 100mv.

> did they see the JEDEC violation after calibration?

Yes. You can see the JEDEC violation.

Refer to "ODT_On_Off" sheet in i.MX6DQ_DDR3_ODT_ON-OFF_rev.3.xlsx.

==On Custom board==

The minimum voltage looked 1.009V with the DDR ODT --> ON (RTT_Nom = RZQ/4  &  RTT_WR = RZQ/4).

And the difference was seen 300mV at the normal temperature.

==On SABRE-SDP==

The minimum voltage looked 1.072V with the BSP setting.

And the difference was seen 391mV at the normal temperature.

I changed my questions.

[Q1]

Is this behavior by i.MX6DQ? (Depend on CPU?)

(We don't think the layout issue. And the behavior wasn't seen in i.MX6SDL.)

[Q2]

Is it possible to improve this phenomenon by register or other one?

Best Regards,

Keita

[Yuri]

Keita, hello !

  Results of measurements on i.MX6 SDP board from app team :

1, the signal amplitude of DQ/DQS does be changed with the DDR ODT on or off,

    so change the ODT setting will affect the tDS parameter. Please be noticed, we    
    guarantee the 80% minimum voltage output in case DDR ODT is off.

2, customer may use the wrong reference voltage to calculate the tDS, from the    
    JEDEC, the tDS calculation should be based on (VREF/2+135mv), so the calculation    
    baseline should be about 800mv, not 900mv customer did.

Regards,
Yuri.

[keitanagashima]

Dear Yuri,

Hello. Thank you for your reply.

>2, customer may use the wrong reference voltage to calculate the tDS, from the    

>    JEDEC, the tDS calculation should be based on (VREF/2+135mv), so the calculation    

>    baseline should be about 800mv, not 900mv customer did.

Refer to "Table 72 — Derating values DDR3-800/1066/1333/1600 tIS/tIH - ac/dc based - Alternate AC150 Threshold" in EDEC Standard No. 79-3F.

VIH(ac) = VREF(dc)+150mV = 750mV + 150mV = 900mV

So, your formula looks wrong.

Please confirm again.

And, please answer the below question.

[Q1]

Is this behavior by i.MX6DQ? (Depend on CPU?)

(Was it possible to confirm the same phenomenon on your environment?)

We don't think the layout issue. And the behavior wasn't seen in i.MX6SDL.

Best Regards,

Keita

[Yuri]

Hello,

  App team wrote : " we didn't find the parameter violation on SDP board".

In particular, tDS min = 125 ps in iMX6 Datasheet. JEDEC specs provide
several options for speed grade and the AC voltage levels in order to meet
timing requirements. It is only required, that  the signals satisfy at least one
set of voltage / timing paratemers.

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

Do you have any update?

The only 1st access amplitude on DQ lines was lower than other access in burst write mode.

Let us clarify the phenomenon caused by i.MX6 or layout.

[Q1]

Did you confirm the same phenomenon on SABRE-SDB board?

[Q2]

Is this phenomenon by the behavior of i.MX6DQ?

Best Regards,

Keita