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iMX283 custom board - loading Linux fails

Question asked by Johan de Jong on Aug 26, 2015
Latest reply on Sep 10, 2015 by Johan de Jong

Dear all,

 

We have a custom board, iMX283 with Alliance Memory AS4C32M16D2-25BCN (DDR2, 64MB, 512Mbit, 1 bank, 16 bits wide databus) memory connected to it (6-layer board, device is just 4mm away from microcontroller). The board runs off a 5V supply, with only the memory connected to the 1.8V power rail (DCDC_VDDA). The power rail is fed by the DCDC converter, which seem to work nice, as the power of the rail increases from 1.78 to 1.81V when switching from the linear regulators to the DCDC converter.

 

In the imx-bootlets code, I modified the EMI clock to run 100MHz, just to be sure memory clock speed is not the problem (fractional divider 480 * 18/29 = 297, integer division factor 6). On the scope it gives, even with a passive probe, a nice non-distorted signal.

 

I'm trying to built updater_ivt.sb using LTIB.

 

In the bootlet code (init-mx28.c) I implemented a small DDR memory test program, which writes 0xAA and 0x55 to memory locations, and reads them back (starting address is 0x40000000, which is DDR base address). This seems to work fine, as the first 1024 locations are written with alternating values, and are read back correctly.

 

However, after the last JUMP instruction to the vector table, the program does nothing anymore. This is the point where I don't known how to proceed.

 

The results of running sb_loader.exe /f updater_ivt.sb are:

---------------------------------------------------------------------------------------

HTLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLFLC

PowerPrep start initialize power...

Battery Voltage = 0.00V

No battery or bad battery detected! Disabling battery voltage measurements.

LLLC

Aug 26 2015 14:52:21

Powering on PLL...

Setting EMI pins...

Setting EMI clock...

CLKCTRL_FRAC0 register value: 0x92925D52

Powering on VDDA...

Changing CPU frequency...

POWER_VDDDCTRL register value: 0x00820710

CLKCTRL_FRAC0 register value: 0x92925D52

Changing CPU frequency to 454MHz...

Starting to change CPU frequency...

CLKCTRL_FRAC0 register value: 0x92925D13

CLKCTRL_HBUS register value: 0x00000003

CLKCTRL_CPU register value: 0x00010001

CLKCTRL_EMI register value: 0x00000106

Wait for DDR2 ready...

Start DDR2 memory test...

DDR2 mapped at 0x40000000. Testing first 0x00000400 memory locations...

Writing memory locations to 0x000000AA, 0xFFFFFF55...

Reading back memory locations...

Writing memory locations to 0x00000055, 0xFFFFFFAA...

Reading back memory locations...

Finished simple test successfully.

LLLLLLLFLCLFLLJ

---------------------------------------------------------------------------------------

(The number 0x000000AA shoud read 0xAA, I'll fix that later)

 

I can run sb_loader.exe as often as I wish, it produces everytime the same results. The voltages (VDD5V, DCDC_VDDD, DCDC_VDDA, DCDC_VDDIO look OK without interruptions/spikes/etc on the oscilloscope. So I assume the power is OK.

 

The ./ltib command produces this table for the loader:

---------------------------------------------------------------------------------------

  LOAD..... (cut away some lines)

  LOAD | adr=0x00001ffc | len=0x00000038 | crc=0x67df6bf0 | flg=0x00000000

  LOAD | adr=0x00002034 | len=0x00000008 | crc=0x13925bb6 | flg=0x00000000

  LOAD | adr=0x0000203c | len=0x000000bc | crc=0xc55a359b | flg=0x00000000

  LOAD | adr=0x000020f8 | len=0x0000008c | crc=0x8a2bdeb8 | flg=0x00000000

  LOAD | adr=0x00002184 | len=0x000000b0 | crc=0xbbe9473a | flg=0x00000000

  LOAD | adr=0x00002234 | len=0x00000040 | crc=0xd84aa7b4 | flg=0x00000000

  LOAD | adr=0x00002274 | len=0x00000030 | crc=0x8912c8f6 | flg=0x00000000

  LOAD | adr=0x000022a4 | len=0x00000038 | crc=0x8b44b847 | flg=0x00000000

  LOAD | adr=0x000022dc | len=0x00000010 | crc=0x332a6bad | flg=0x00000000

  LOAD | adr=0x000022ec | len=0x00000048 | crc=0xcd5ea097 | flg=0x00000000

  LOAD | adr=0x00002334 | len=0x0000002c | crc=0xdc5b5aa9 | flg=0x00000000

  LOAD | adr=0x00002360 | len=0x00000005 | crc=0x763cab7d | flg=0x00000000

  FILL | adr=0x00002368 | len=0x00000024 | ptn=0x00000000

  LOAD | adr=0x00008000 | len=0x00000020 | crc=0x0ec9b2e5 | flg=0x00000000

  CALL | adr=0x00008000 | arg=0x00000000 | flg=0x00000001 <----- start executing power_prep

  LOAD | adr=0x00000000 | len=0x00000c10 | crc=0x6bd0b098 | flg=0x00000000

  LOAD | adr=0x00000c10 | len=0x00000320 | crc=0x620fd097 | flg=0x00000000

  LOAD | adr=0x00008000 | len=0x00000020 | crc=0x7ebfbf46 | flg=0x00000000

  CALL | adr=0x00008000 | arg=0x00000000 | flg=0x00000001 <----- start executing boot_prep

  LOAD | adr=0x00002000 | len=0x00000144 | crc=0xea80477d | flg=0x00000000

  LOAD | adr=0x00002160 | len=0x0000078c | crc=0xf6d80ca0 | flg=0x00000000

  LOAD | adr=0x00002900 | len=0x00000004 | crc=0xdc0472d0 | flg=0x00000000

  LOAD | adr=0x00002920 | len=0x00000008 | crc=0x55e1b86b | flg=0x00000000

  LOAD | adr=0x00002928 | len=0x00000028 | crc=0x3c146c50 | flg=0x00000000

  LOAD | adr=0x00002960 | len=0x000000ec | crc=0x7e0b4612 | flg=0x00000000

  LOAD | adr=0x00002a60 | len=0x000000d8 | crc=0x1388eb32 | flg=0x00000000

  FILL | adr=0x00002b40 | len=0x00000014 | ptn=0x00000000

  LOAD | adr=0x00008000 | len=0x00000020 | crc=0x38d66e8d | flg=0x00000000

  CALL | adr=0x00008000 | arg=0x00000000 | flg=0x00000001 <----- start executing linux_prep

  LOAD | adr=0x40008000 | len=0x0014d6fc | crc=0xf1b7c167 | flg=0x00000000 <----- loads zImage into DDR memory (~1.3MB, free space is almost 8MB)

  FILL | adr=0x40800000 | len=0x00600000 | ptn=0x00000000 <----- clear some memory locations

  LOAD | adr=0x40800000 | len=0x0049684a | crc=0xc4f78213 | flg=0x00000000 <----- loads initramfs into DDR memory (~4.7MB)

  LOAD | adr=0x00008000 | len=0x00000020 | crc=0x38d66e8d | flg=0x00000000 <----- load vector table

  JUMP | adr=0x00008000 | arg=0x00000000 | flg=0x00000001 <----- jump into just loaded vector table

---------------------------------------------------------------------------------------

 

Can anyone help me out?

For example with code I can load to test if it is executed correctly from DDR memory? Is the JUMP instruction just wrong? Did I miss any patches?

 

I've looked into all DDR2 memory initialisation topics from Freescale community already, and filled in the Excel sheet with timing parameters. And because the DDR memory test routines work well, I thing that is not the problem anymore.

 

If you need more information, please let me know.

Thanks in advance.

Outcomes