Using the MPC5644A, when the core issues the "wait" instruction without having previously set SIU_HLT[CPUSTP], we have observed that the core and DMA stops. Indeed, the e200z4 core RM does not seem to say there is a condition for the core enter low-power mode. However, the MPC5644A RM says in the SIU_HLT register description that "In the case of the CPU, stop mode in entered when the corresponding bit in SIU_HLT is set and a WAIT instruction is executed." This tends to say BOTH must be set (wait + CPUSTP) for the core/DMA to do in low-power mode.
If that's true (core+DMA goes into low-power mode with only the "wait" instruction), then what's the purpose of the CPUSTP bit...?
Side question: is it possible to halt only the core without halting the DMA/XBAR/RAM/PBRIDGE/STM?