Quting e200z4 Power Architecture™ Core Reference Manual, Rev. 0, chapter 8.2:
Waiting State
The e200 core enters the waiting state as a result of executing a wait instruction. Following entry into the
waiting state, instruction execution and bus activity is suspended. Most internal clocks are gated off in this
state. The e200 core asserts p_waiting to indicate it is in the waiting state. Prior to entering the waiting
state, all outstanding instructions and bus transactions will be completed. The m_clk input should remain
running while in the waiting state to allow for interrupt sampling, and to allow further transitions into the
Halted or Stopped state if requested and to keep the Time Base operational if it is using m_clk as the clock
source.
In the waiting state, the core is waiting for a valid unmasked pending interrupt request. Once a pending
interrupt request is received, the core will exit the waiting state and begin interrupt processing. The return
program counter value will point to the next instruction after the wait instruction. The interrupt can be an
external input interrupt, various critical interrupts, a debug interrupt (based on ICMP), a non-maskable
interrupt, or a machine check interrupt (p_mcp_b assertion, etc.). Once the interrupt processing begins,
the core will not return to the waiting state until another wait instruction is executed.
The waiting state can be temporarily exited and returned to if a request is made to enter hardware debug
mode (various mechanisms), the halted state, or the stopped state. After exiting one of these states, the
processor will return to the waiting state. While temporarily exited, the p_waiting output will negate, and
will be re-asserted once the CPU returns to the waiting state.
