Would you tell me the specifications of REF_CLK generated internally?
We think about the configuration that REF_CLK is output by FEC_REF_CLK pin.
This is configuration explained in Figure 11-3 of IMX6SLHDG.
- Figure 11-3. Internal reference clock(P.106)
We want to know the contents similar to specifications explained in "Table 52.RMII Signal Timing" of the data sheet.
- Table 52. RMII Signal Timing(P.65)
(We understand that it is a timing specification of REF_CLK when it is input to FEC_TX_CLK pin.)