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Reading clock rate value and the actual measured value are differenc for the LVDS clock signal on Yocto

Question asked by charles huang on Aug 25, 2015
Latest reply on Jul 13, 2016 by jim.lin

I refer to the following URL.

Reference URL: https://community.freescale.com/thread/306801

 

I set a frequency of 29.5 MHz for the PLL5 LVDS clock signal on Yocto 3.10.17.1.0.2, the value is close to 29.5 MHz by oscilloscope.

But the clock rate value of pll5 video is close 206.5 MHz on console log.

 

Console log:

# cat /sys/kernel/debug/clk/osc/pll5_video/pll5_post_div/pll5_video_div/clk_rate

206499990

#  cat /sys/kernel/debug/clk/osc/pll5_video/pll5_post_div/pll5_video_div/ldb_di0_sel/clk_rate

206499990

 

Can you tell me why reading clock rate value and the actual measured value are difference?

 

Thank you.

 

Best Regards,

Alex Cheng

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