Configuration problem with fsl_sdcard driver component

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Configuration problem with fsl_sdcard driver component

Jump to solution
552 Views
matheuspinto
Contributor II

Hi,

I am trying to use the fsl_sdcard component with KDS 3.0.0 and PE, and the eval boards FDRM K22F and FRDM-KL25Z.

err6.png

Using the FRDM-K22F, the inherited component is added:

err3.png

But a problem occurs in the fsl_dspi component. Is not accepted any clock value, like you can see in figure below:

err2.png

Even using the timing dialogue box, to choose a predetermined clock, doesn't work:

kkk.png

The same problem occurs using FRDM KL25Z, however, the inherited component add is the fsl_spi.

err4.png

err5.png

Any advice?

0 Kudos
1 Solution
368 Views
Jorge_Gonzalez
NXP Employee
NXP Employee

Hello Matheus Pinto:

When you create a project for a board (e.g. FRDM-K22F) Processor Expert provides a set of predefined clock configurations. You can analyze such configurations by opening the settings of the fsl_clock_manager component.

For example the "clockMan1_InitConfig5" corresponds to a Core clock = 100 Mhz and Bus clock = 50 MHz:

pastedImage_4.png

In the top of the timing dialog box for fsl_dspi you can see that all the clock configurations are enabled by default:

pastedImage_2.png

In that case the SPI clock frequency must be achievable with all clock configurations using dividers and prescalers.

To resolve this you can simply disable the configurations that you will not use. e.g. I enabled only Clock cfg. 5 and this lets me set the frequency to 400 kHz:

pastedImage_3.png

I hope this helps. Let me know if you have questions.

Regards!,
Jorge Gonzalez

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
2 Replies
369 Views
Jorge_Gonzalez
NXP Employee
NXP Employee

Hello Matheus Pinto:

When you create a project for a board (e.g. FRDM-K22F) Processor Expert provides a set of predefined clock configurations. You can analyze such configurations by opening the settings of the fsl_clock_manager component.

For example the "clockMan1_InitConfig5" corresponds to a Core clock = 100 Mhz and Bus clock = 50 MHz:

pastedImage_4.png

In the top of the timing dialog box for fsl_dspi you can see that all the clock configurations are enabled by default:

pastedImage_2.png

In that case the SPI clock frequency must be achievable with all clock configurations using dividers and prescalers.

To resolve this you can simply disable the configurations that you will not use. e.g. I enabled only Clock cfg. 5 and this lets me set the frequency to 400 kHz:

pastedImage_3.png

I hope this helps. Let me know if you have questions.

Regards!,
Jorge Gonzalez

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
368 Views
matheuspinto
Contributor II

Thanks Jorge,

It worked!

0 Kudos