Dear Freescale TIC,
We want to fine-tune High width and Low width of SDCLK.
We found that High width and the Low width of the clock were changed by changing DO_TRIM field and DO_TRIM_PADN field.
- 35.5.199 Pad Control Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P (P.1936-)
However, we were not able to find detailed explanation about DO_TRIM field and DO_TRIM_PADN field.
Would you tell me the usage of these field?
Can we use it to fine-tune High width and Low width of SDCLK?