AnsweredAssumed Answered

IPU v3  CSI input with FV (Frame Valid) instead of VSYNC in gated clock mode.

Question asked by Austin Phillips on Aug 21, 2015
Latest reply on Aug 22, 2015 by Austin Phillips

Hello,

 

I am using an imx6 to capture data from a parallel Aptina MT9P031 camera via the CSI0 interface in gated clock mode.  As per other discussions in this forum, I've modified the Linux Freescale driver to support capturing 16 bit generic data through CSI->MEM.

 

Some captured frames appear to be a combination of two frames indicating a vertical synchronisation issue.  The MT9P031 camera uses a Line Valid (LV) signal and Frame Valid (FV) signal instead of a single HSYNC and VSYNC pulse indicating the start of a line/frame.  The FV signal remains active through the entire frame transfer and so does not match the timing diagrams shown in the imx6 RM which indicate HSYNC/VSYNC as having a single pulse.

 

The following thread indicates that for HSYNC, only the leading edge is important to determine the start of a line. IPU v3  CSI0, HSYNC and DATA_EN questions in gated clock mode.

 

Does the same apply for the VSYNC input?  ie Is the VSYNC input treated as an edge triggered or level triggered signal?

 

If this is a level triggered input, what is the suggested method to connect sensors which utilise line/frame valid signals instead of hsync/vsync inputs?

 

Thank you

Austin

 

Message was edited by: Austin Phillips Corrected title to specify frame valid rather than line valid

Outcomes