PLL error with a bad Reset

[JasminG_]

If the vcc drop to 1.25V on my PCB de LVD do a reset but the PLL timing is wrong after the reset.
The timing for UART is corrupt.

Wath is the register corrupt the PLL on bad reset.

Jasmin.

[JWW]

Jasmin,

Which ColdFire part are you using?

Some of the PLLs come up with a default setting that you might be overriding by accident with a Codewarrior init (which is what you perceive to be the correct operation), and after a reset your code is not setting up the PLL the same way that Codewarrior does and therefore your baud rate is no longer correct.

So if you could provide a few more details then we may be able to help.

1. Which ColdFire part.
2. Which debugger and IDE are you using.
3. Are you using any of the free pieces of code like Linux or CMX stack or I-niche stack?

Thanks
-JWW

[JasminG_]

The IC is MCF52235CAL60.
The IDE is Codewarior for Coldfire 6.4 in WinXP.
I use a Bacnet Stack and a Ethernet Stack.
Jasmin.

[JasminG_]

Ok, I found the bug.
It's necesary to enable the pll before disable.
After this you write the new value and re-enable the PLL.

This error is present in the code source with M52235EVB.
At the first boot the value dosn't load.
After a bad reset the PLL in enable and the code disable correctly the PLL.

In the fact if I don't put the bad value in PLL in acordance with the code coments, I never found the error.

Bye.

[JasminG_]

static void mcf5223x_pll_init(void) {
    //MCF_CLOCK_CCHR = 0x05; // The PLL pre divider -> 25MHz / 5 = 5MHz (This is wrong)

    /* The PLL pre-divider affects this!!!
     * Multiply 25Mhz reference crystal /CCHR by 12 to acheive system clock of 60Mhz
     */

    MCF_CLOCK_SYNCR = 0
        //|MCF_CLOCK_SYNCR_LOLRE    // No reset on Loss Of Lock
        | MCF_CLOCK_SYNCR_MFD(4)    // CLK * 12
        | MCF_CLOCK_SYNCR_RFD(0)    // CLK / 1
        //| MCF_CLOCK_SYNCR_LOCRE    // No reset on Loss Of Clock
        //| MCF_CLOCK_SYNCR_LOCEN    // Loss Of Clock Disabled
        //| MCF_CLOCK_SYNCR_DISCLK    // CLKOUT Enabled
        //| MCF_CLOCK_SYNCR_FWKUP    // Wait PLL is locked
        | MCF_CLOCK_SYNCR_CLKSRC    // PLL Drive System Clock
        | MCF_CLOCK_SYNCR_PLLMODE    // PLL Mode
        | MCF_CLOCK_SYNCR_PLLEN;    // PLL Enabled (this is absolutely necesary to do enable before)

    MCF_CLOCK_CCHR = MCF_CLOCK_CCHR_CCHR(4); // The PLL pre divider -> 25MHz / 5 = 5MHz (This is Good)

    // Reset PLL to use CCHR (and Disable and RE-Enable)
    MCF_CLOCK_SYNCR &= ~MCF_CLOCK_SYNCR_PLLEN;
    MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_PLLEN;

    while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK)) {
        // PLL not locked
    }
}

Bye and good luck all.