Hi,
Marek Neuzil was kind enough to provide a working SDRAM example for Processor Expert. He posted it here: Re: can't read data back from SDRAM.
I modified it slightly to get some time measurement into it for better benchmarking of the SDRAM performance.
Unfortunetly, the numbers I get are worse than expected.
I'm getting arround 57 MB/s of memset performance.
I would expect something that is derived from a theoretical value of 240 MB/s (60 MHz bus clock x 32 Bit Buswidth)
Peter,
The system bus is used for all accesses to addresses between 0x2000_0000-0xDFFF_FFFF and 0xE010_0000-0xFFFF_FFFF by the Core. Therefore the system cache can be used for caching of SDRAM data that are accessed by using 0x7000_0000–0x7FFF_FFFF or 0x8000_0000–0x8FFF_FFFF addresses (R7 and R8 cache regions).
Best Regards,
Marek Neuzil