Does Sabre Quad board have any memory limitation?

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Does Sabre Quad board have any memory limitation?

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ivyliu
Contributor IV

Hi All,

I have a Sabre Quad board with1G DDR memory.

Because our own board will just have 256M memory, I want to do some mem setting test on the Linux kernel with Sabre Quad board.

I use "mem=" to change kernel's memory size .

The linux kernel 3.14.28 can work with memory setting that is equal to or bigger than 512M.

But it does not work with any setting that is smaller than 512M, I tried 256M, 320M and 448M.

none of them can work.

I have removed the GPU and Crypto CAAM which are in the OOPs from the kernel, but the kernel still can not run.

Is there any memory size limitation in 3.14.28 kernel?

pc : [<00000000>]    lr : [<80036a60>]    psr: 20000113

sp : 8c093eb8  ip : 8c093ee0  fp : 00000000

r10: 00000000  r9 : 8c032814  r8 : 00000000

r7 : 8c092038  r6 : 00000101  r5 : 8c092000  r4 : 8c032000

r3 : 8c093eb8  r2 : 00000101  r1 : 00000000  r0 : 00000000

Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel

Control: 10c53c7d  Table: 1000404a  DAC: 00000015

Process swapper/1 (pid: 0, stack limit = 0x8c092238)

Stack: (0x8c093eb8 to 0x8c094000)

3ea0:                                                       00000000 8fdce3c0

3ec0: 8c032000 8c093ee0 00200200 00000000 80d320c0 80036c50 8c032a14 8c032c14

3ee0: 8c093ee0 8c093ee0 9cc2a69d 00000000 80d32084 00000101 8c092000 80d32080

3f00: 80d32080 00000001 40000001 80030be8 9cc2a69d 00000000 9cc2a69d 80d2d458

3f20: 00000001 0000000a 80d98dc0 80d320c0 ffff8bd8 8c092010 806b03d8 00200040

3f40: 802a87c0 8c092028 0000001d 00000000 f4a00100 8c092000 80d96c7d 8c092000

3f60: 8c092000 80030fac 80d2de54 8000eccc f4a0010c 80d38970 8c093f98 80008598

3f80: 8000f024 8000f010 60000113 ffffffff 8c093fcc 80012140 ffffffed 0f0a1000

3fa0: 80d392c0 8001cb20 80d38574 806b03cc 8c092000 80d96c7d 8c092000 80d96c7d

3fc0: 8c092000 8c092000 00000000 8c093fe0 8000f024 8000f010 60000113 ffffffff

3fe0: 00000000 80066438 8000864c 80d97188 00000000 10008664 6d718244 f5742030

[<80036a60>] (call_timer_fn.isra.33) from [<80036c50>] (run_timer_softirq+0x18c/0x208)

mmc3: new high speed DDR MMC card at address 0001

mmcblk3: mmc3:0001 SEM08G 7.39 GiB

mmcblk3boot0: mmc3:0001 SEM08G partition 1 1.00 MiB

mmcblk3boot1: mmc3:0001 SEM08G partition 2 1.00 MiB

mmcblk3rpmb: mmc3:0001 SEM08G partition 3 128 KiB

[<80036c50>] (run_timer_softirq) from [<80030be8>] (__do_softirq+0x10c/0x248)

[<80030be8>] (__do_softirq) from [<80030fac>] (irq_exit+0xb8/0xf4)

[<80030fac>] (irq_exit) from [<8000eccc>] (handle_IRQ+0x44/0x90)

[<8000eccc>] (handle_IRQ) from [<80008598>] (gic_handle_irq+0x2c/0x5c)

[<80008598>] (gic_handle_irq) from [<80012140>] (__irq_svc+0x40/0x70)

Exception stack(0x8c093f98 to 0x8c093fe0)

3f80:                                                       ffffffed 0f0a1000

3fa0: 80d392c0 8001cb20 80d38574 806b03cc 8c092000 80d96c7d 8c092000 80d96c7d

3fc0: 8c092000 8c092000 00000000 8c093fe0 8000f024 8000f010 60000113 ffffffff

[<80012140>] (__irq_svc) from [<8000f010>] (arch_cpu_idle+0x2c/0x44)

[<8000f010>] (arch_cpu_idle) from [<80066438>] (cpu_startup_entry+0x104/0x150)

[<80066438>] (cpu_startup_entry) from [<10008664>] (0x10008664)

Code: bad PC value

---[ end trace 6e349054cbd0fb29 ]---

Kernel panic - not syncing: Fatal exception in interrupt

Thanks and Best Regards,

Ivy

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ivyliu
Contributor IV

Hi All,

I have fixed this problem.

There is a 320M reserved to DMA contiguous memory.

I changed it to 96M, then it works.

I just wonder is 96M enough for IPU, VPU and GPU?

Why the original kernel code choose 320M to reserve? is there any requirement?

Thanks and Best Regards,

Ivy

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ivyliu
Contributor IV

Hi ALL,

I just heard that GPU has some memory reserved.

Does VPU & IPU has memory reservation too?

Does this cause the problem?

Thanks and Best Regards,

Ivy

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ivyliu
Contributor IV

Hi All,

I have fixed this problem.

There is a 320M reserved to DMA contiguous memory.

I changed it to 96M, then it works.

I just wonder is 96M enough for IPU, VPU and GPU?

Why the original kernel code choose 320M to reserve? is there any requirement?

Thanks and Best Regards,

Ivy

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Rita_Wang
NXP TechSupport
NXP TechSupport

Hi Ivy,

I am very glad you have solved your problem. Welcome to create new threads in our community, any questions you can contact us.

Have a nice day

Best Regards

Dan

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