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DDR Stress Test Failed

Question asked by Bruce Sun on Aug 7, 2015

Hi,

 

We make a board based on i.mx6dlsabreauto but failed for DDR stress test. For DDR component we use MT41K256M16HA-125:E. Can anybody help me with this issue?

 

Bruce

 

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        DDR Stress Test (2.0.0)

        Build: Jun 11 2015, 23:33:58

        Freescale Semiconductor, Inc.

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        Chip ID

DIGPROG(0x020c8260) = 0x00610002

CHIP ID = i.MX6 Solo/DualLite (0x61)

Internal Revision = TO1.2

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        Boot Configuration

SRC_SBMR1(0x020d8004) = 0x5a003242

SRC_SBMR2(0x020d801c) = 0x31000001

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ARM Clock set to 1GHz

 

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        DDR configuration

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is DDR3

Data width: 64, bank num: 8

Row size: 15, col size: 10

Chip select CSD0 is used

Density per chip select: 2048MB

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Current Tempareture: 52

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DDR Freq: 396 MHz

 

ddr_mr1=0x00000000

Start write leveling calibration...

running Write level HW calibration

Write leveling calibration completed

    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0051004E

    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x0045004C

    MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x002D002D

    MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x0028003D

Write DQS delay reult:

   Write DQS0 delay: 78/256 CK

   Write DQS1 delay: 81/256 CK

   Write DQS2 delay: 76/256 CK

   Write DQS3 delay: 69/256 CK

   Write DQS4 delay: 45/256 CK

   Write DQS5 delay: 45/256 CK

   Write DQS6 delay: 61/256 CK

   Write DQS7 delay: 40/256 CK

 

Starting DQS gating calibration

. . . . . . . . . . . . . . ERROR FOUND, we can't get suitable value !!!!

dram test fails for all values.

 

Error: failed during ddr calibration

Original Attachment has been moved to: ddr_calibration_20150807-11'54'44.log.zip

Original Attachment has been moved to: MX6DL_ARD_DDR3_register_programming_aid_v0.2.inc.zip

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