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Question about SBC MC33908 Failsafe release mechanism

Question asked by Hoang Nguyen on Aug 6, 2015
Latest reply on Mar 7, 2017 by Andrew Smith

Hi all,

I'm integrating this SBC IC into an ECU system. Currently i'm having some confusions on the mechanism to release the Failsafe line (FS0b) after start-up, or wakeup from LPOFF mode. From my understanding, after waking up, the FS line is asserted (LOW) and the Reset Error Counter is 1. To release the FS line, i need to service the WD 7 consecutive times (assuming the WD refresh counter is kept at default value - 6). My system currently has a defined task used to service the WD at 100ms period (WD windows is configured at 128ms). Using this approach though, i will need 700ms after waking up to release the FS, which is way too long and unacceptable in my system.I'm thinking of 2 possible solutions:

- Change the WD refresh counter to 1. With this setting, it'll take 2 good WD refresh to release the FS line, which takes 200ms. This number is still way too slow and i would prefer a much shorter time to release the FS line.

- Change the WD windows to 3ms, service the WD using timer interrupt, then after the FS line is released, i'll need to change the WD windows back to 128ms so the OS task can be used to pet the dog. This would satisfy the requirement but seems overly complicated to me and may cause synchronization issue in the system as well.

My question is should there be a better solution to this? What is the regular mechanism that is being used to release the FS line?