I want to control i.MX6's SDMA like following.
Two device is connected on EIM.
I want to use SDMA for low-speed interface to reduce CPU workload. But FPGA does not have a FIFO memory. It can receive only 1 byte. So SDMA speed is limited by low-speed interface. I am afraid of bus busy by burst DMA with low-speed interface.
I have three questions.
1. Can I change burst size of SDMA for EIM?
2. Can I use peripheral DMA for EIM devices?
3. Can FPGA control SDMA access by changing a level of SDMA_EXT_EVENT after SDMA is triggerd?