Hello Adam,
You are using Processor Expert and fsl_spi component. There is important to properly set the fsl_spi component and the initialization. You must properly set (enable) the
Master configuration, enable the Auto Initialization and set the Master configuration in the initialization (the Processor Expert generate spi device initialization code as a part of the PE_low_level_init() function - fsl_spi driver initialization functions are called in the ComponentsInit() function).
You must also enable and select used pins (these pins are disabled by default). See the screenshot below:
Best Regards,
Marek Neuzil
Adam,
I have checked the reference manual, FRDM-KL03Z scheme and everything is OK (PTA6 and PTA7 pins are not used by other devices). I have also created the target board application that work properly - SCK and MOSI signals are OK (data are sent). See the following picture of the board and used pins:
You can check the attached application that works on my FRDM-KL03Z target board properly.
When you connect PTA6 and PTA7 by a wire data are sent and received correctly in the application (see the connection on the picture above).
Note:
I am not using Tabs view in the Component Inspector window and therefore the view is different. If you want to use the same tree view navigate into Component Inspector window, open the menu and uncheck the Tabs view, see the screenshot below:
Best Regards,
Marek Neuzil
Adam,
I have checked the driver that is designed for transferring block of data. I have measured the delay between two characters when the bock of 10 bytes is sent and there were 100us delay only (I have used the modified demo application).
There is CPU time consuming interrupt service routine and the SPI does not have any FIFO buffer. If you want to reduce the delay between characters you can increase the bus clock (and core clock). When I have used bus clock 24MHz and core clock 48MHz, the delay is about 10us.
Note:
The bus clock and core clock frequency can be set in the fsl_clock_manager component in the project. Open the Component Inspector of the component, select the MIRC in the MCG mode property and set the Core clock to 48MHz and Bus clock to 24MHz, see the screenshot below:
If you need a simple SPI driver for your application and you cannot use high bus/core clock frequencies you can use Init_SPI and fsl_spi_hal components to write a simple driver that meets requirements of your application.
Best Regards,
Marek Neuzil
Marek,
I have confirmed that the pins were both configured as well as the SPI module was also initialized. I have included a few screen grabs to show that this is the case. I also am wondering why my configuration screen is different than what you showed in yours. Even if I set it to advanced, I do not get the same configuration screen. More of a curiosity than anything else. I am running the stock KDS 3.0 with integrated Pex and KSDK 1.2.
Also note that I have included a screen capture of the my logic analyzer showing the clock doing what it should, but the data lines being silent.
Adam
