We are trying to support a new camera on CSI0 (parallel sensor interface). Our sensor works in ITU601 mode that looks like the "gated" mode, except that HSYNC is active during the complete duration of an image (starting 16 pixel clock cycles before the first HSYNC gets active, and stopping 16 pixel clock cycles after the last HSYNC gets inactive).
It doesn't match with the normal usage of the gated mode (described at §220.127.116.11.2 of the RM) but should work if the VSYNC is edge-triggered (either on the rising or the falling edge).
If the level of VSYNC is taken into account, it probably won't work.
Has anyone used gated mode with a similar signal VSYNC ?
Is there any internal information on GATED MODE indicating if such a VSYNC signal could also work ?
Thanks for any feedback.