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How to understand if Memory Reservation is completly implemented in a Multi Core (Multi Master) MCU.

Question asked by Errico Guidieri on Jul 27, 2015
Latest reply on Jul 29, 2015 by Errico Guidieri



for my multicore application I need to implement a finer grained locking mechanism, respect to which I can implement with SEM4 module (read: I need more than 16 locks).


Playing with some platforms I discovered that, even though all the implemented e200 cores (maybe with the exception of e200z0), implement the Book E "Memory Reservation" mechanism, not all the "memory controllers" mounted on MCUs generate the p_rsrv_clr needed to use this mechanism in a multi core (multi master) environment [the environment where this feature is more useful].


For my experience what I saw is that MCUs equipped with only e200z7 (like MPC5777C Cobra55) Cores have the memory controller that support this mechanism, whereas MCU equipped with e200z4 too (Like MPC5777M) do not.


But I couldn't find any evidence of this on MCUs' user manual. In general I would like to know, reading manuals, if such features is supported or not.


Where and what I need to check?



Thank you,

Errico Guidieri