- What is the clock source for the internal Ethernet Switch to FMan MAC1/MAC2 interfaces working at fixed 2.5 G rate – SerDes PLL2 or Platform PLL? May I leave the SD1_REF_CLK2_P/N pins unconnected and power down the SerDes PLL2 (if e.g. SRDS_PRTCL_S1=0x69 and SATA interface is not used) and still use that aggregate 5 Gbps (2x 2.5 Gbps) link between Ethernet Switch and FMan?
- T1040 RM says that recommended setting for RCW[FM1_MAC_RAT] (FM1-to-MAC1 Ratio) is 1 (“at least one of the MAC’s is operating at 2.5G interface”). There is no external 2.5G interfaces in T1040. Is this recommendation applicable to the internal Switch to FMan interfaces?
- Figure 4-23 “Single Oscillator Source Clocking” in T1040 RM shows that the duty cycle corrector supplies the 125 MHz clock to MAC1 and MAC2 blocks in the FMAN. Should these blocks be named as EC1 and EC2 indeed? May I leave both (EC1/EC2)_GTX_CLK125 pins unconnected if MII and RGMII interfaces are unused and the deep sleep feature is not implemented?
- What is the functional difference between RCW[MAC2_GMII_SEL] and SCFG_ESGMIISELCR.GMIISEL fields?