Please let me know the instruction set are same for e200z0 and e200z7 core. If the compiler supports for e200z0 based SOC the same one will support for e200z7 based SOC.
Basic VLE instruction set is the same (note that z7 also support BookE) but there are several possible differences given by
1) presence of EFPU/SPE
2) also instructions specified by Engineering Bulletin “New VLE Instructions for Improving Interrupt Handler Efficiency” are not present on all e200 cores (however there are present on all z7 and z0 cores):
These instruction only affects ISRs and can be enabled by following pragma:
Note that this pragma without vle_multiple option means these instruction will not be used:
3) also there are possible difference not given by instruction set, but core differences itself. Understandably you cannot configure cache with core that does not have cache, for instance.
Some e200 core comparison:
I compared e200z0 and e200z7 reference manuals. I observed the instructions mfdcr, mtdcr1,bcctrl,stbcx and few other are not supported in e200z0 but it is supported in e200z7
I'm using PowerPC MPC5553. I'm compiling an application that uses setjmp/longjmp. The code compiles fine but when executing the code.It runs for several cycles in which setjump/longjump being called for context switching. Below are the macro being called in application.#define RTS_CPU_STORE_CONTEXT(context, piResult) /*lint -e64 */(*((int*)piResult) = setjmp(context))#define RTS_CPU_RESTORE_CONTEXT(context, parameter) longjmp(context, parameter)There after Controller get memory crash & does not give even watchdog reset.
So in above case as wll I should use __declspec(interrupt vle_multiple) as in setjump macro is uses the VLE instruction?
If yes then where to declare above macro?
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