I am designing with the K22FX512AVLQ12 in mind. I have a memory interface I put together based on what I understood of the FLEXBUS in the K22P144M120SFV2RM.pdf reference manual. However I have seen several comments in Freescales community boards about problems people are having using a x16 bit data bus. AN4393 doesn't talk about using a non-multiplexed interface for a x16 bit data bus. So, before I make a board, I wanted someone to advise me that this design will work, and if there are other limitations with it if it does. For example, can it read/write an odd or even byte without affecting the corresponding even or odd byte? Will a 32-bit aligned read or write actually result in two memory cycles to the SRAM? Will non-aligned reads and writes work? If the design does work, it should be added to AN4393.
Also, Table-4-1 of the reference manual shows the FLEXBUS to be in 5 different regions of the memory map. The comments I have seen recommend using the "External Peripheral" space. "write-back" and "write-through" suggests a cache, but there is no mention of a cache for the FLEXBUS in the reference manual.