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i.mx6s DQS gating calibration ERROR FOUND

Question asked by rao dejian on Jul 18, 2015
Latest reply on Jul 20, 2015 by rao dejian

Hi,

 

My i.mx6 core board has DDR issue when running stress tester, it’s similar with other people’s who discussed in old thread. The difference is Quad and Dual can working with 1.2GHz processor and DDR stress test up to 628MHz, when I replace the processor by Solo or DualLite on same core board then the DQS gating calibration issue occurred.


I am confused does there any hardware issue made this strange issue? My test conditions as below,

  1. DDR Stress Tester: V2.0-RC1 and v1.0.3
  2. Core board configuration:

     * CPU: MCIMX6S5EVM10AB/AC silicon version v1.2

     * DDR RAM: MT41K256M16HA-125:E 2pcs

     * DDR RAM: MT41K128M16JT-125 IT:K 2pcs

     *i-NAND: SDIN7DU2

     *PMU: MMPF0100-F0EP

3. The core board follow Freescale SDP reference design

4. i.MX6DQSDL DDR3 Script Aid V0.10

5. DDR Stress Tester log

222.jpg

============================================
        DDR Stress Test (2.0.0)
        Build: Jun 11 2015, 23:33:58
        Freescale Semiconductor, Inc.
============================================

============================================
        Chip ID
DIGPROG(0x020c8260) = 0x00610002
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.2
============================================

============================================
        Boot Configuration
SRC_SBMR1(0x020d8004) = 0x020078f0
SRC_SBMR2(0x020d801c) = 0x22000001
============================================

ARM Clock set to 1GHz

============================================
        DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 32, bank num: 8
Row size: 14, col size: 10
Chip select CSD0 is used
Density per chip select: 512MB
============================================

Current Tempareture: 43
============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00440049
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x003A003F
Write DQS delay reult:
   Write DQS0 delay: 73/256 CK
   Write DQS1 delay: 68/256 CK
   Write DQS2 delay: 63/256 CK
   Write DQS3 delay: 58/256 CK

Starting DQS gating calibration
. . . . . . . . . . . . . . ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration

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