On a custom host board for a Variscite SoM we're attempting to use the S/PDIF transmitter for an application requiring a fairly high degree of clock precision. Notably the default configuration for the S/PDIF transmitter clock under Linux (using the linux-fslc tree) is to source the SPDIF0 clock from PLL3 PFD3, leaving it as the closest candidate when the S/PDIF transmitter driver selects a clock source. It is however, not accurate enough for our purposes, being off by fractions of a percent, rather the dozen PPM or so we need.
From what I could dig up, the use of that PFD for the SPDIF0 clock rather than the audio PLL is hard-coded into the clock driver, however changing it to the post-divided audio PLL output did not result in it being selected, rather the clock source chosen at the last mux (SPDIF_STC's TxClk_Source) was now the divided ipu_clk rather than tx_clk (SPDIF0_CLK_ROOT). I believe this was because of a failure to correctly set the intermediary dividers, as the combination of defaults for the other dividers and the range of PLL4 is outside of the divider range for only the S/PDIF transmitter divider.
My question then is how would I go about configuring the clock system under Linux to allow those intermediary dividers (ANALOG_PLL_AUDIO's POST_DIV_ SELECT, MISC2's AUDIO_DIV_LSB/_MSB, and CDCDR's SPDIF0_CLK_PRED and SPDIF0_CLK_PODF) to factor in to clock selection such that PLL4 with its fractional divider can be used to output S/PDIF with the precision we need? I have acquired accurate frequencies under Linux by manually poking registers via /dev/mem from userspace, however that's obviously highly undesirable.