I have implemented a design that uses PCIe. It is somewhat different in that the PCIe interface is used as a chip-to-chip communication lane on a single PCB (e.g. no PCIe connector).
The root complex device is a Freescale i.MX6 Dual which is PCIe Gen 2 compliant and the device I am communicating with is a Marvell WiFi module that is a PCIe Gen 3 compliant device. It's a single lane interface running at 2.5Gbps.
I've done some signal integrity measurements by soldering a high speed scope with proper differential probes right on the other side of the inline caps shown below. The total link/route length is about 2.5 inches. The i.MX6 is on a SOM while the WiFi module is on a PCB I designed. About half of the channel routing distance is on the SOM and the rest on the carrier board. The coupling caps are placed near the WiFi module which probably increasing the amount of reflections.
For the clock the eye diagram looks quite good:
But the TX data not so much:
The WiFi chip has on-chip terminations so I don't believe I am supposed to need any additional terminations, but I could be wrong about that.
We are in FULL SWING mode and set the register to the max value. We have played with the PCIe Gen 1 value and the above eye represents about the best we can find at 6'h7. It seems like each of the DEEMPH registers do the same thing and so the actual one that is selected may not matter.
I've checked that the layout follows proper routing rules and the PCB was constructed with the correct impedance. The coupling caps are 0402 in size. Obviously I have some jitter in the system but it also looks like I have a reflection or de-emphasis issue. I'm hoping someone could describe what they see wrong with my eye diagram and/or suggest some ways to fix it.
NoteL We are not entering into compliance mode and just doing this testing on the standard link traffic. If we force entry into compliance mode via software the eye diagram actually gets worse but it also looks like it messes with a number of the other channel settings.