AnsweredAssumed Answered

Executing i.MX6 Solo X M4 core from TCM

Question asked by ANDREW WAYNER on Jul 15, 2015
Latest reply on Jul 15, 2015 by Jas Math

1) Section 13.5 of the reference manual discusses the Cortex-M4 boot requirements. In particular it states that the A9-core is responsible for "...setting up Cortex-M4 initial exception table in TCRAML". The application note AN5127 only specifies how to run the MQX code from QSPI (default from bundle), DDR, or OCRAM. There is no mention of how to execute code from TCRAML. Please provide instructions on how to do this.

 

2) I tried to determine what address the A9-core would use to write to the TCRAML (prior to enabling the M4 core). Table 2-1 does not specify a System memory region for accessing the TCRAML from the A9 core. There is talk about a "backdoor" access port for the A9 to write to this memory, but no description on how to do so that I could find. All my attempts to try to write to this memory have failed (doing so from the U-boot command line prompt using the "cp" command). Please advise on the correct procedure to allow the A9 core to write to the M4 core's TCM prior to enabling the M4 core.

Outcomes