AnsweredAssumed Answered

atomic operations

Question asked by lwn on Jul 15, 2015
Latest reply on Jul 16, 2015 by Scott Wood

Hello,

 

Accessing shared memory from multiple cores in a SMP systems can be tricky. Disabling the caching for shared memory regions would be possible but very slow. Using atomic operations to access shared memory regions appears to be more reasonable in a SMP system.

 

a)

We were looking for 64bit atomic integer load/store in the e5500 Core Reference Manual. However, this appears to be not possible on PPC32 as ldarx/stdcx conditional instructions are only available on PPC64.

Is there some alternative, we are missing?

 

b)

Are 64bit floating point load/store operations lfd*/ stfd* always atomic on PPC32 (e5500 core)?

There appear to be no conditional instructions for floating point load/store. How is that safely handled between multiple cores in a SMP system?

 

Thanks

Outcomes